The alternative method of obtaining in CMOS technology of a PTAT2 current generator is based on implementing a computational circuit for realizing the squaring function using MOS transistors biased in saturation region. The relatively small errors for both types of circuits are a consequence of the independence of output current on technological parameters. Supposing a saturation operation of all transistors, the circuit from Fig.

The translinear loop is characterized by the following equation: 2VGS. Considering that all MOS transistors from Fig. Because V potential represents the arithmetic mean of VO and V1 potentials fixed by IO and I currents, respectively , the expression of I2 current could be written as follows: 4K. Current mirrors from Fig.

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The first method is based on the design of a translinear loop using bipolar or MOS transistors biased in weak inversion, the number of series transistors biased at the PTAT input current IIN being equal with n. The characteristic equation of the translinear loop is as follows: nVBE. The disadvantage of this method is the necessity of a relatively large value of the supply voltage, with a minimum value of nVBE C VCEsat , restricting the utilization domain of these circuits.

In order to obtain a circuit accepting a reasonable value of the minimum supply voltage, the nth order power of the input current could be implemented in many 34 1 Current References Fig. The squaring circuit can be symbolized as shown in Fig. The first squaring circuit implements the function: IOUT. References 1. Wiley, New York 2. Huang Shizhen et al.

Wiley, New York 4. The 27th Edition Annual Semiconductors Conference — Chapter 2 Zero-Order Curvature-Corrected Voltage References Abstract Presenting the advantage of simplicity, zero-order curvature-corrected voltage reference circuits exhibit a relatively large value of the temperature coefficient. For bipolar technology, base—emitter voltage and Zener voltage represent the most common approach for designing CTAT voltage references; the difference between two base—emitter voltages being the usual method for implementing PTAT voltage references.

The area of application for zero-order curvature-corrected voltage reference is related to the basic circuits that not require a very small value of the temperature coefficient, representing, also, the basis from developing first-order and superior-order curvature-corrected voltage references with a much better temperature behavior. Additionally, PTAT voltage references could be used as absolute temperature sensors in the hypothesis of a high linearity of their temperature dependence. Zero-order compensated voltage references present the advantage of simplicity, their performances being relatively poor.

The temperature dependence of the collector current is supposed to be polynomial, IC. The logarithmical dependence VBE. Using 2. Considering the function f. The simulation of the base—emitter voltage temperature dependence is presented in Fig. A circuit that generates a reference voltage equal with the base—emitter voltage is presented in Fig. The self-biasing of the T3 —T4 core, realized using the current mirror T1 —T2 permits to reduce the dependence of reference voltage on supply voltage.

It results in VREF. The self-biasing of the T3 —T4 core, realized using the current mirror T1 —T2 , improves the power supply rejection ratio. This circuit generates a voltage, which is equal, in a first-order approximation, with the threshold voltage of MOS devices or with a multiple of this voltage. The additional taking into account of the second-order effects that influence the MOS transistor operation mobility degradation, bulk effect and channel-length modulation evidentiates errors that affect the linearity of the reference voltage temperature dependence.

The concrete method for obtaining the threshold voltage is based on the computing of weighted difference between gate— source voltages of MOS transistors biased in saturation. Expressing the gate—source voltages as functions of drain currents supposing a biasing in saturation of all MOS active devices and disregarding, in a first-order approximation, the second-order effects, it is possible to write s 2ID1;2 VGS1;2 D VT C : 2. In order to reduce the minimum supply voltage, the standard circuits additionally require minimum values of constants a and b, so a D 2 and thus, b D 1, resulting in.

The simulation of temperature dependence of reference voltage is presented in Fig.

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For determining the output voltage of threshold voltage extractor, VREF , it is necessary to originally find the expression of V voltage. An alternate application of the PTAT voltage sources is the utilization of these circuits as temperature sensors. The additional possibility to introduce the sensor in a negative reaction loop permits to obtain a high value temperature coefficient, and therefore, a very good sensitivity with respect to the temperature variations for the output voltage.

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The Bipolar Offset Voltage Follower Block The usual method to obtain a PTAT voltage presumes to consider the difference between two base—emitter voltages of bipolar transistors biased at different current densities. A possible implementation of this principle is presented in Fig. The expression of the reference voltage remains the same relation 2. The expression of the current through R1 resistor will be IR1. The simulation of temperature dependence of IR1 current is presented in Fig. The additional considering of channel-length modulation effect for T5 and T6 transistors leads to modification of the relation 2.

The assembly formed from R3 ; D1 , and D2 represents the start-up circuit of reference voltage, having the role to take out from initial status, characterized by null currents. The minimization of the occupied area by PTAT voltage generator can be realized by replacing all resistors from the circuit with active devices.

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Figure 2. Considering that T1 and T2 transistors have. R2 ln. A circuit similar to that from Fig. A possible implementation of a PTAT generator using the difference between two gate—source voltages and an operational amplifier is presented in Fig. Wiley, NY 2. The 24th European Solid-State Circuits Conference — Chapter 3 First-Order Curvature-Corrected Voltage References Abstract An important improvement of the voltage references temperature behavior compared with previously analyzed zero-order curvature-corrected circuits can be achieved by implementing a first-order curvature-correction technique.

The common method for designing these structures is based on compensating the approximate linear decrease with temperature variations of base—emitter, gate—source, or threshold voltages by a complementary PTAT voltage voltagemode approach.

## [volt-nuts] Superior-Order Curvature-Correction Techniques for Voltage References

An alternative implementation of the same principle, presenting the advantage of allowing a low-voltage operation is based on a current-mode operation of the voltage reference, a PTAT current compensating the negative linear decreasing with temperature of a current derived from a base—emitter, gate—source, or threshold voltages.

The starting point in designing a voltage reference with superior performances is represented by a voltage having an important variation with temperature, of CTAT type, generated by a zeroorder compensated voltage reference. The linear dependence on temperature term from the expression of this voltage will be compensated by a complementary PTAT term, this technique being named linear or first-order curvature-correction of the voltage reference.

The presence in the expression of the reference voltage of some terms with a nonlinear variation with temperature limits the possibility of reduction of the temperature coefficient of the reference voltage by the exclusive implementation of the linear curvature-correction, an additional improvement of temperature behavior of the voltage reference imposing the design of a superior-order curvaturecorrection technique Chap. The temperature coefficient of the voltage that resulted following correction will present relatively high values as a consequence of the logarithmical dependence on temperature term from VBE.

There are two possibilities for designing this type of voltage reference. The first possibility uses identical T1 and T2 transistors and T6 —T7 current mirror with over unitary transfer factor,. Considering an operation in saturation of the MOS transistors, it results in the following design condition:. It is also possible, evidently, to obtain the design of a version with double asymmetry, owing to the both transistor pairs, useful for obtaining a PTAT current with high-value temperature coefficient.

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But, in CMOS technology, the obtaining of bipolar transistors as parasite devices requires the utilization of a much greater silicon area than the area necessary for a MOS transistor, with the utilization of bipolar transistors with as reduced as possible area being preferable. The first design possibility will be studied, considering the fulfilled relation 3. Consider the voltage reference from Fig. The simulation for the temperature dependence of IR1 current is presented in Fig.

Consider that T2 and T4 transistors have areas n times greater than areas of T1 and T3 transistors. The simulation of the temperature dependence of the I current is presented in Fig. The condition for linear curvaturecorrection of the reference voltage is as follows: VBE. The circuit from Fig.

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The elimination of necessity for utilization of VC1 and VC2 external potentials can be realized by using the circuit from Fig. The illustration of this principle is presented in Fig.

Consider the reference voltage from Fig. According to relation 3. Following to the I1. The realization of the linear curvature-correction imposes to be fulfilled in relation 3.